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cmos 8-bit single chip microcomputer description the CXP820P60 is a cmos 8-bit single chip microcomputer integrating on a single chip an a/d converter, serial interface, timer/counter, time-base timer, capture timer/counter, fluorescent display panel controller/driver, remote control reception circuit, and pwm output circuit besides the basic configurations of 8-bit cpu, rom, ram, and i/o port. the CXP820P60 also provides sleep/stop function that enables lower power consumption. CXP820P60 is the prom-incorporated version of the cxp82052/82060 with bult-in mask rom. this provides the additional feature of being able to write directly into the program. thus, it is most suitable for evaluation use during system development and for small-quantity production. features wide-range instruction system (213 instructions) to cover various types of data ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 250ns at 16mhz operation 122s at 32khz operation incorporated prom capacity 60k bytes incorporated ram capacity 3984 bytes (including fluorescent display area) peripheral functions ?a/d converter 8 bits, 8 channels, successive approximation method (conversion time of 3.25s/16mhz) ?serial interface incorporated buffer ram (auto transfer for 1 to 32 bytes), 1 channel 8-bit clock synchronized type, (msb/lsb first selectable), 1 channel start-stop synchronization (uart), 1 channel ?timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer 16-bit capture timer/counter, 32khz timer/counter ?fluorescent display panel supports the universal grid fluorescent display panel controller/driver high voltage drive output port of 56 pins (40v) maximum of 640 segments display possible display timing number of 1 to 20 dimmer function incorporated pull-down resistor (mask option) hardware key scan function (maximum of 16 8 key matrix supportable) ?remote control reception circuit 8-bit pulse measurement counter, 6-stage fifo ?pwm output 14 bits, 1 channel interruption 17 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp piggy/evaluation chip cxp82000 100-pin ceramic qfp ?1 e97638a1y-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP820P60 100 pin qfp (plastic) structure silicon gate cmos ic
?2 CXP820P60 8-bit timer/counter 0 8-bit timer 1 uart baud rate generator uart receiver uart transmitter int2 xtal pwm ram 3984 bytes spc 700 cpu core a/d converter int3/nmi int1 int0 an0 to an7 8 pa0 to pa7 fdp controller/ driver 32khz timer/counter prescaler/ time-base timer rst v dd v ss port a port b port c port d port e port f port g 8 8 6 2 8 8 8 8 pb0 to pb7 pc0 to pc7 pd0 to pd7 pe0 to pe5 pf0 to pf7 pg0 to pg7 pe6 to pe7 tex extal tx cs0 2 prom 60k bytes ram key scan port h ph0 to ph7 8 clock generator/ system control 14-bit pwm generator fifo remocon rmc si0 so0 sck0 si1 so1 sck1 ec0 to cint ec1 adj g0/a0 to g15/a15 a16 to a23 a24 to a56 v fdp kr0 to kr7 16 8 32 8 2 serial interface (ch1) 16-bit capture timer/counter 2 serial interface (ch0) buffer ram 2 2 port i pi0 to pi4 4 txd rxd interrupt controller ram vpp block diagram
3 CXP820P60 pin assignment (top view) g1/a1 g0/a0 vpp pe0/ec0/int0 pe1/ec1/int1 pe2/int2 pe3/int3/nmi pe4/rmc pe5/cint pe6/pwm pe7/to/adj pc0/kr0 pc1/kr1 pc2/kr2 pc3/kr3 pc4/kr4 pc5/kr5 pc6/kr6 pc7/kr7 pb0/txd pb1/cs0/rxd pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pi0 pa0/an0 pa1/an1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 81 82 83 84 75 76 77 78 88 87 86 85 79 80 89 90 10 0 99 98 97 96 95 94 91 92 93 1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 pa6/an6 pa7/an7 pi1 rst extal xtal vss pi2/tx pi3/tex v dd v fdp pd0/a55 pd1/a54 pd2/a53 pd3/a52 pd4/a51 a21 a22 a23 ph7/a24 ph6/a25 ph5/a26 ph4/a27 ph3/a28 ph2/a29 ph1/a30 ph0/a31 pg7/a32 pg6/a33 pg5/a34 pg4/a35 pg3/a36 pg2/a37 pg1/a38 pg0/a39 pf7/a40 pf6/a41 pf5/a42 pf4/a43 pf3/a44 pf2/a45 pf1/a46 pf0/a47 pd7/a48 pd6/a49 pd5/a50 g2/a2 g3/a3 g4/a4 g5/a5 g6/a6 g7/a7 g8/a8 g9/a9 g10/a10 g11/a11 g12/a12 v dd g13/a13 g14/a14 g15/a15 a16 a17 a18 a19 a20 note) 1. vpp (pin 3) is left open. 2. v dd (pins 44 and 89) are both connected to v dd .
4 CXP820P60 pin description symbol i/o functions i/o/ analog input pa0/an0 to pa7/an7 (port a) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of the pull-up resistor can be set through the program in a unit of 4 bits. (8 pins) analog inputs to a/d converter. (8 pins) i/o/input pc0/kr0 to pc7/kr7 pe0/int0/ ec0 pe1/int1/ ec1 pe2/int2 pe3/int3/ nmi pe4/rmc pe5/cint pe6/pwm pe7/to/ adj input/input/input input/input/input input/input input/input/input input/input input/input output/output output/output/ output (port c) 8-bit i/o port. i/o can be set in a unit of single bits. capable of driving 12ma sink current. incorporation of the pull-up resistor can be set through the program in a unit of 4 bits. (8 pins) serves as key return inputs when operating key scan with fluorescent display panel (fdp) segment signal. (8 pins) i/o/output pd0/a55 to pd7/a48 (port d) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) fdp segment signal (anode connection) outputs. (port e) 8-bit port. lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) external event inputs for timer/counter. (2 pins) inputs for external interruption request. (4 pins) non-maskable interruption request input. remote control reception circuit input. external capture input for 16-bit timer/counter. 14-bit pwm output. output for the 16-bit timer/counter rectangular waves, and 32khz oscillation frequency division. i/o/output i/o/input/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input i/o/output pb0/txd pb1/cs0/rxd pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of the pull-up resistor can be set through the program in a unit of 4 bits. (8 pins) uart transmission data output. chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1). uart reception data input.
5 CXP820P60 (port f) 8-bit output port. i/o can be set in a unit of single bits. (8 pins) fdp segment signal (anode connection) outputs. (8 pins) symbol i/o functions output a16 to a23 fdp segment signal (anode connection) outputs. (8 pins) output/output g0/a0 to g15/a15 outputs for fdp timing signals (grid connection)/segment signals (anode connection). (16 pins) output/output ph0/a31 to ph7/a24 input pi0 input pi1 input pi2/tx input/input pi3/tex output/output pg0/a39 to pg7/a32 (port h) 8-bit output port. (8 pins) (port i) 4-bit input port. (4 pins) v fdp extal xtal rst vpp v dd v ss input fdp voltage supply for incorporated pull-down (pd) resistor. crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. low-level active, system reset. vcc supply for incorporated prom writing. leave this pin open during normal operation. positive power supply. gnd. fdp segment signal (anode connection) outputs. (8 pins) crystal connectors for 32khz timer/counter clock oscillation. for usage as event counter, input to tex, and leave tx open. (port g) 8-bit output port. (8 pins) fdp segment signal (anode connection) outputs. (8 pins) input pf0/a47 to pf7/a40 i/o/output
6 CXP820P60 i/o circuit format for pins ? pull-up transistor approx. 100k ? pull-up registor port b data port b direction "0" after a reset rd (port b) internal data bus ip ? "0" after a reset uart output selection "0" after a reset txd ip pull-up registor port b data port b direction "0" after a reset rd (port b) internal data bus ? pull-up transistor approx. 100k ? ? "0" after a reset schmitt input cs0 si0 si1 rxd port b 8 pins hi-z hi-z after a reset pa0/an0 to pa7/an7 1 pin pb0/txd pb1/cs0/rxd pb3/si0 pb6/si1 port b 3 pins hi-z ip pull-up registor port a data port a direction "0" after a reset port a input selecton "0" after a reset rd (port a) internal data bus a/d converter ? pull-up transistor approx. 100k ? ? input multiplexer "0" after a reset input protection circuit port a pin circuit format
7 CXP820P60 2 pins hi-z hi-z pin after a reset circuit format pb4/so0 pb7/so1 pc0/kr0 to pc7/kr7 8 pins ip pull-up registor port c data port c direction "0" after a reset rd (port c) internal data bus ? 1 large current 12ma ? 2 pull-up transistor approx. 100k ? ? 2 "0" after a reset ? 1 key input signal ? pull-up transistor approx. 100k ? pull-up registor port b data port b direction "0" after a reset rd (port b) internal data bus ip ? "0" after a reset serial data output enable port b outputput selecton "0" after a reset so port c port b ? pull-up transistor approx. 100k ? pull-up registor port b data port b direction "0" after a reset rd (port b) internal data bus ip ? "0" after a reset schmitt input sck in serial clock output enable port b output selecton "0" after a reset sck out port b 2 pins hi-z pb2/sck0 pb5/sck1
8 CXP820P60 pin after a reset circuit format 1 pin pe7/to/adj ? 1 adj signal is a frequency dividing output for 32khz oscillation frequency adjustment. adj2k can be used for buzzer output. ? 2 pull-up transistor approx. 150k ? port e data "00" after a reset ? 2 to output enable to adj16k ? 1 adj2k ? 2 00 01 10 11 mpx internal reset signal port e output selecton (upper) port e output selecton (lower) "1" after a reset port e 16 pins hi-z pd0/a55 to pd7/a48 pf0/a47 to pf7/a40 port d port f high level (high level at on resistance of pull-up transistor during a reset) ? high voltage drive transistor rd (port d and f) internal data bus ? "1" after a reset port d and f data port d and f direction segment output data output selection control signal ("0" after a reset) ip ? 1 pin pe6/pwm port e output selecton port e data rd (port e) internal data bus "1" after a reset "0" after a reset pwm output enable port e high level 6 pins hi-z pe0/ec0/int0 pe1/ec1/int1 pe2/int2 pe3/int3/nmi pe4/rmc pe5/cint ip schmitt input internal data bus ec0/int0 ec1/int1 int2 int3/nmi rmc cint rd (port e) port e
9 CXP820P60 hi-z pg0/a39 to pg7/a32 ph0/a31 to ph7/a24 port g port h rd (port g and h) internal data bus output selection control signal ("0" after a reset) port g and h data "0" after a reset segment output data ? ? high voltage drive transistor 16 pins pin after a reset circuit format 16 pins g0/a0 to g15/a15 2 pins 2 pins extal xtal oscillation hi-z pi0 pi1 hi-z or low level (when pd resistor is connected) output selection control signal ("0" after a reset) segment output data timing output data ? ? high voltage drive transistor pull-down registor v fdp 8 pins a16 to a23 hi-z or low level (when pd resistor is connected) output selection control signal segment output data ? ? high voltage drive transistor pull-down registor v fdp ("0" after a reset) extal xtal ip ip diagram shows circuit composition during oscillation. feedback resistor is removed and xtal becomes high level during stop. ip rd (port i) internal data bus
10 CXP820P60 pin after a reset circuit format 2 pins oscillation stop port input low level pi2/tx pi3/tex 1 pin rst aa a ip aa aa pi3/tex pi2/tx a ip tex oscillation circuit control "1" after a reset internal data bus rd internal data bus rd clock input ip schmitt input pull-up registor
11 CXP820P60 ? 1 v in , v out and v od must not exceed v dd + 0.3v. ? 2 v fdp and v od must not exceed v dd 40v. ? 3 specifies output current of general-purpose i/o ports. ? 4 the large current drive transistor is the n-ch transistor of port c (pc). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. supply voltage fdp display supply voltage input voltage output voltage display output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd vpp v fdp v in v out v od i oh i odh1 i odh2 i oh i odh i ol i olc i ol topr tstg p d 0.3 to +7.0 0.3 to +13.0 40 ? 2 to +7.0 ? 1 0.3 to +7.0 ? 1 0.3 to +7.0 ? 1 40 ? 2 to +7.0 ? 1 5 15 50 30 120 15 20 100 20 to +75 55 to +150 600 v v v v v v ma ma ma ma ma ma ma ma c c mw incorporated prom all pins excluding display outputs ? 3 (value per pin) display outputs a20 to a55 (value per pin) display outputs g0/a0 to g15/a15, and a16 to a19 (value per pin) total for all pins excluding display outputs total for all display outputs pins excluding large current output (value per pin) large current output pins ? 4 (value per pin) total for all output pins item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
12 CXP820P60 low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.7 0.4 +75 v v v v v v v v v v v v c item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 0.7v dd 0.8v dd 0.7v dd v dd 0.4 0 0 0 0.3 20 v ih v ihs v ihh v ihex v il v ils v ilh v ilex topr guaranteed operation range during 1/2, 1/4 frequency dividing clock modes guaranteed operation range during 1/16 frequency dividing clock or sleep modes guaranteed operation range with tex clock guaranteed data hold range during stop ? 1 ? 2 ? 3 extal ? 4 ? 1 ? 2 ? 3 extal ? 4 v dd ? 1 value for each pin of normal input port (pa, pb0, pb4, pb7, pc). ? 2 value of the following pins: rst, cint, cs0/rxd, si0, si1, sck0, sck1, ec0/int0, ec1/int1, int2, int3/nmi, rmc. ? 3 value for each pin (pd, pf). ? 4 specifies only during external clock input. recommended operating conditions (vss = 0v reference) high level input voltage
13 CXP820P60 v dd = 4.5v, i oh = 0.5ma v dd = 4.5v, i oh = 1.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 4.5v, v il = 4.0v v dd = 4.5v v oh = v dd 2.5v v dd = 5.5v v ol = v dd 35v v fdp = v dd 35v v dd = 5v v od v fdp = 30v v dd = 5.5v v i = 0, 5.5v high level output current display output current 4.0 3.5 0.5 0.5 0.1 0.1 1.5 3.3 8 30 30 v v v v v a a a a a a a ma ma a k ? a pc pa to pd, pe6, pe7, pf to ph pa to pc, pe6, pe7 extal tex rst item symbol pins conditions min. pa to pc ? 1 a20 to a55 g0/a0 to g15/a15, a16 to a19 g0/a0 to g15/a15, a16 to a55 g0/a0 to g15/a15, a16 to a23 pa to pc ? 1 , pd ? 2 , pe0 to pe5, pf ? 2 , pi i oh open drain output leakage current (p-ch tr off state) i lol pull-down resistance i/o leakage current r l i iz v oh v ol i ihe i ile i iht i ilt i ilr i il low level output current input current 70 typ. 0.4 0.6 1.5 40 40 10 10 400 50 20 220 10 max. unit dc characteristics electrical characteristics (ta = 20 to +75 c, v ss = 0v reference)
14 CXP820P60 item symbol pins conditions min. typ. max. unit supply current ? 3 input capacity v dd pa to pc, pd ? 2 , pe0 to pe5, pf ? 2 , pi, extal, rst i dd1 1/2 frequency dividing clock mode operation i dds1 i dds2 i dds3 i dd2 v dd = 5.5v, 16mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) sleep mode stop mode v dd = 5.5v, termination of 16mhz and 32khz oscillation v dd = 5.5v, 16mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) 27 55 ma 35 110 a 1.5 8 ma 15 30 a 10 a c in clock 1mhz 0v for all pins excluding measured pins 10 20 pf ? 1 pa to pc pins specify the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. ? 2 pd and pf pins specify when they are used as input pins by program. ? 3 when all pins are open.
15 CXP820P60 extal t xh t xl t cf t cr 0.4v v dd 0.4v 1/fc aaaa aaaa aaaa aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 aaaa aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 tex ec0 ec1 t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr ? 1 t sys indicates the three values below according to the upper two bits (cpu clock selection) of the control clock register (clc: 00feh). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise time, fall time event count input clock pulse width event count input clock rise time, fall time system clock frequency event count input pulse width event count input rise time, fall time f c t xl t xh t cr t cf t eh t el t er t ef f c t tl t th t tr t tf xtal extal extal extal ec0, ec1 ec0, ec1 tex tx tex tex mhz ns ns ns ms khz s ms item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 28 t sys + 50 ? 1 10 typ. 32.768 max. 16 200 20 20 (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 2. clock applied conditions fig. 1. clock timing fig. 3. event count clock timing
16 CXP820P60 chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the control clock register (clc: 00feh). t sys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") note 2) the load condition for the sck0 output mode, so0 output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item cs0 sck0 delay time cs0 sck0 float delay time cs0 so0 delay time cs0 so0 float delay time cs0 high level width sck0 cycle time sck0 high, low level width si0 input setup time (for sck0 ) si0 input hold time (for sck0 ) sck0 so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc 50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit condition
17 CXP820P60 cs0 sck0 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 0.2v dd fig. 4. serial transfer ch0 timing
18 CXP820P60 sck1 0.2v dd 0.8v dd t kl t kh so1 t kcy t sik t ksi 0.2v dd 0.8v dd t kso 0.2v dd 0.8v dd output dat input data si1 serial transfer (ch1) (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item sck1 cycle time t kcy sck1 input mode ouput mode input mode ouput mode sck1 input mode sck1 ouput mode sck1 input mode sck1 ouput mode sck1 input mode sck1 ouput mode 1000 16000/fc 400 8000/fc 50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns sck1 si1 si1 so1 t kh t kl t sik t ksi t kso sck1 high, low level width si1 input setup time (for sck1 ) si1 input hold time (for sck1 ) sck1 so1 delay time symbol pin condition min. max. unit note) the load condition for the sck1 output mode, so1 output delay time is 50pf + 1ttl. fig. 5. serial transfer ch1 timing
19 CXP820P60 conversion time sampling time analog input voltage t conv t samp v ian v zt ? 1 v ft ? 2 an0 to an7 ta = 25 c v dd = 5.0v v ss = 0v linearity error zero transition voltage full-scale transition voltage resolution s s v v dd 26/f adc ? 3 6/f adc ? 3 0 item symbol pin condition min. typ. max. unit bits (3) a/d converter characteristics (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 8 3 lsb 70 mv 5030 10 4970 10 4910 mv fig. 6. definition of a/d converter terms analog input linearity error v ft v zt 00h 01h feh ffh digital conversion value ? 1 v zt : value at which the digital conversion value changes from 00h to 01h and vice versa. ? 2 v ft : value at which the digital conversion value changes from feh to ffh and vice versa. ? 3 f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (adc: 00f9h) and bits 7 (pck1) and 6 (pck0) of the clock control register (clc: 00feh). however, the selection for f adc = f c (cks = "0") is limited in the clock range of f c = 1 to 14mhz (v dd = 4.5 to 5.5v).
20 CXP820P60 0.2v dd 0.8v dd t ih t il t il t ih int0 int1 int2 nmi/int3 (nmi specifies only for the falling edge.) t rsl 0.2v dd rst external interruption high, low level width reset input low level width int0 int1 int2 nmi/int3 rst 1 32/fc s s item symbol pin condition min. max. unit t ih t il t rsl (4) interruption, reset input (ta = 20 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 7. interruption input timing fig. 8. rst input timing
21 CXP820P60 appendix c 1 aaaa aaaa extal xtal c 2 aaaa aaaa extal xtal rd (i) main clock aaaa aaaa extal xtal c 1 c 2 rd xtal (ii) main clock aaaa aaaa extal xtal c 1 c 2 rd aaaa aaaa tex tx (iii) sub clock fig. 9. recommended oscillation circuit models marked with an asterisk ( ? ) have the built-in ground capacitance (c 1 , c 2 ). manufacturer river eletec co., ltd murata mfg co., ltd. csa10.0mtz csa12.0mtz csa16.00mxz040 cst10.0mtw ? cst12.0mtw ? cst16.00mxw0c1 ? kinseki ltd. seiko instruments inc. model hc-49/u03 hc-49/u (-s) vtc-200 sp-t fc (mhz) 10.0 12.0 16.0 10.0 12.0 16.0 8.0 12.0 16.0 8.0 12.0 16.0 30 5 30 5 18 12 10 10 5 open 18 30 5 30 5 18 12 10 10 5 open 18 0 330 0 32.768khz 330k (iii) c 1 (pf) c 2 (pf) rd ( ? ) circuit example (i) (i) (ii) c l = 12.5pf remarks mask option table item package rom capacitance reset pin pull-up resistor high voltage drive pin pull-down resistor 100-pin plastic qfp 52k/60k byte existent/non-existent existent/non-existent 100-pin plastic qfp prom 60k byte existent non-existent (ph7/a24 to pd0/a55) existent (g0/a0 to a23) mask rom CXP820P60q-1-
22 CXP820P60 characteristics curve 10 1 0.1 0.01 100 012 3 4567 i dd vs. v dd v dd supply voltage [v] i dd supply current [ma] 1/4 dividing mode sleep mode 1/16 dividing mode 32khz mode 32khz sleep mode 1/2 dividing mode 0 5 10 15 20 0 5 10 15 20 25 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode sleep mode i dd vs. fc fc system clock [mhz] i dd supply current [ma]
23 CXP820P60 package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy package structure 23.9 0.4 qfp-100p-l01 100pin qfp (plastic) 20.0 0.1 + 0.4 0.15 0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 0.1 + 0.4 2.75 0.15 + 0.35 a 0.65 m 0.13 qfp100-p-1420 1.7g 1 100 81 80 51 50 31 30 0.3 0.1 + 0.15 detail a 0 ? to 10 ? 0.8 0.2 (16.3) 0.15 0.1 0.05 + 0.2 lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. sony corporation

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